The present invention relates, generally, to the field of microelectronic packaging, and more particularly relates to provision of a compliant interface between microelectronic elements such as a semiconductor chip and substrate.
Designers and manufacturers of electronic devices are continually searching for ways to reduce the size of electronic components. Some recent developments involve the use of solder connections for electrically interconnecting semiconductor chips to printed circuit boards (xe2x80x9cPCBxe2x80x9d) in order to use the space on the PCB more efficiently. Solder connections have proven to be somewhat effective; however, the differences in thermal expansion and contraction (xe2x80x9cthermal mismatchxe2x80x9d) between the semiconductor chip and the PCB places a great amount of stress on the solder and may adversely effect the integrity of the numerous solder bonds required to make an electrical connection. Warpage of either the semiconductor chip or the PCB may also have a negative effect on the integrity of the solder connections.
There have been a number of prior art solutions attempting to reduce the stress on solder joints caused by thermal mismatch. One solution put forth in U.S. Pat. No. 4,642,889 teaches embedding wires within each solder column to reinforce the solder, thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth in U.S. Pat. No. 5,316,788 includes providing a combination of solder and high-lead solder. Still other prior art solutions make use of an underfill material disposed between the semiconductor chip and the supporting substrate which allows the stress caused by the thermal mismatch to be more uniformly spread out over the entire surface of the solder connection. All of these prior art solutions are aimed at improving the reliability of solder connections; however, each of these solutions encounters significant problems such as insufficient compliancy between the semiconductor chip and the PCB
Several inventions, commonly assigned to the assignee of the present invention, deal effectively, with the thermal mismatch problem. For example, U.S. Pat. No. 5,148,266 discloses improvements in semiconductor chip assemblies and methods of making the same. In certain embodiments of the ""266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals, which can be bonded to a substrate, are provided on the second surface of the interposer, and the interposer is provided with apertures extending through it. Flexible leads extend through the apertures, between the terminals on the second surface of the interposer and the contacts on the chip. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the ""266 patent provide excellent resistance to differential expansion of the chip relative to the substrate caused by thermal cycling. The interposer disclosed in the ""266 patent may also include a compliant layer disposed between the terminals and the chip.
Commonly assigned U.S. patent application Ser. No. 08/123,882, filed Sep. 20, 1993 (now U.S. Pat. No. 5,477,611), the disclosure of which is incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is a curable material which is cured into a resilient layer such as an elastomer after its introduction into the gap. In a preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Copending, commonly assigned U.S. patent application Ser. No. 08/365,699 entitled xe2x80x9cCompliant Interface for a Semiconductor Chip and Method Thereforxe2x80x9d filed Dec. 29, 1994, the disclosure of which is incorporated herein by reference, discloses a method of fabricating a compliant interface for a semiconductor chip, typically comprised of a compliant encapsulation layer having a controlled thickness. In certain preferred methods according to the ""699 application, a first support structure, such as a flexible, substantially inextensible dielectric film, is provided. A resilient element, such as a plurality of compliant pads, is attached to a first surface of the first support structure, with any two adjacent compliant pads defining a channel therebetween. Attaching the compliant pads to the first support structure may be accomplished in a number of different ways. In one embodiment, a stencil mask having a plurality of holes extending therethrough is placed on top of the first surface of the support structure. The holes in the mask are then filled with a curable liquid, such as a silicone. After the mask has been removed, the curable liquid is at least partially cured to form an elastomer, such as by heating or by exposure to ultraviolet light. Thus, there is provided an assembly which includes a plurality of compliant pads having channels between adjacent pads.
In a further preferred embodiment of the ""699 application, the assembly including the plurality of compliant pads is used with a second support structure such as a semiconductor chip having a plurality of contacts on a first surface. The first surface of the chip is abutted against the plurality of compliant pads and the contacts are electrically connected to a corresponding plurality of terminals on a second side of the support structure. Typically, the first surface of the chip is pressed against the array of compliant pads by a platen engaged with the terminals, thereby assuring the planarity of the first support structure, or flexible dielectric film. A compliant filler such as a curable liquid is then injected into the channels between the chip and the support structure and around the compliant pads while the chip and support structure are held in place. The filler may then be cured to form a substantially uniform, planar, compliant layer between the chip and the support structure. Preferred embodiments of the ""699 application provide a compliant, planar interface which effectively accommodates for the thermal coefficient of expansion mismatch between the chip and a supporting substrate thereby alleviating much of the stress on the connections therebetween. Further, the combination provides an effective encapsulation barrier against moisture and contaminants.
Commonly assigned U.S. Pat. No. 5,548,091 describes other methods of bonding compliant elements to the chip and support structure using adhesives. In certain preferred methods according to the ""091 patent, a support structure such as a dielectric film is provided with a prefabricated compliant layer. The compliant layer in turn has an adhesive on its surface remote from the dielectric film. The semiconductor chip is placed in contact with the adhesive, and the adhesive is activated to bond the chip to the compliant layer. The adhesive may be provided in a non-uniform layer to facilitate release of air during the bonding process and thus prevent void formation. Known adhesives tend to delaminate from the resilient element under the extreme stresses of temperature and humidity and also under stress of extreme thermal mismatch. Accordingly, still further improvements directed toward providing a resilient element that can be more effectively bonded to microelectronic elements using known adhesives would be desirable.
Despite the positive results of the aforementioned commonly owned inventions, the disclosures of which are incorporated herein by reference, still further improvements would be desirable.
One aspect of the present invention provides a method of making microelectronic assemblies. A method in accordance with this aspect of the invention includes the steps of providing first and second microelectronic elements having electrically conductive parts, juxtaposing the first and second elements with one another and bonding electrically conductive parts of the microelectronic elements to one another to form electrical interconnections. For example, the first element may be a flexible dielectric interposer with terminals and leads thereon, whereas the second element may include one or more semiconductor chips having contacts thereon. The leads may be bonded to the contacts so as to connect the terminals with the contacts.
The method also includes the step of providing one or more porous resilient elements having one or more tacky surface regions in contact with one or more liners separately from the first and second microelectronic elements, assembling the resilient elements with at least one of the microelectronic elements and removing the resilient element from the one or more liners prior to the juxtaposing step so that the resilient elements are disposed between the microelectronic elements after the juxtaposing and bonding steps. In accordance with this step, the resilient element is removed from storage and before applying the resilient element to the surface of a first microelectronic element a first liner film is removed from the resilient element to expose a first tacky surface region. In order to reduce the adhesion between the liner and the resilient element, heat may be applied to the liner to soften the tacky surface region of the resilient element in contact with the liner. The resilient element is then assembled to a first microelectronic element so that the first tacky surface region of the resilient element is in contact with the first microelectronic element. The second liner film is then removed from the resilient element to expose a second tacky surface region and the second surface region is then assembled to a second microelectronic element.
The resilient elements may include a tacky material, such as an adhesive, in contact with the first and second tacky surface regions. The tacky material may be provided at the surface regions of the resilient element during fabrication thereof or just prior to assembly of the resilient element with microelectronic elements. Alternatively, the tacky material may be provided on the microelectronic elements themselves prior to their being assembled with the resilient element. In another embodiment, the resilient element is partially-cured and has first and second surface regions which are not fully cured. In this embodiment, the first and second surface regions are in contact with a cure-inhibiting material while the resilient element is in storage. The partially-cured aspect of the present invention incorporates the realization that once a resilient element is fully cured, it is difficult to later effectively bond the resilient element to a microelectronic element. Although the present invention is not limited by any theory of operation, it is believed that these difficulties result from the fact that once a resilient element is fully cured, many adhesives cannot wet to the resilient element and thus the adhesives are unable to chemically bond the resilient element. As a result, there is only surface adhesion between the resilient element and the adhesive and this forms a weak bond between the resilient element and the microelectronic elements. Thus, by providing resilient elements having wettable surface regions, the difficulties associated with creating an effective bond between the resilient element and the adhesive are substantially eliminated.
In other embodiments, the method of making microelectronic assemblies includes providing a resilient element having one or more tacky surface regions separately from first and second microelectronic elements, and assembling the resilient element with at least one of the microelectronic elements prior to the juxtaposing step so that the resilient element is disposed between the microelectronic elements after the juxtaposing and bonding steps. The step of assembling the resilient element with at least one of the microelectronic elements is preferably performed just shortly before the step of bonding the conductive parts to one another, typically less than 24 hours before the bonding step and most preferably less than one hour before the bonding step. This particular aspect of the invention incorporates the realization that the manner in which a resilient element is applied to a microelectronic element can affect the bonding operation. Thus, where resilient elements are applied to a microelectronic element, such as a flexible interposer, and the subassembly is stored for a prolonged period and then assembled to another microelectronic element, difficulties can arise in the bonding process used to join the electrically conductive parts to one another. It is generally accepted that these difficulties result from low-molecular-weight substances included in the resilient element exuding from the resilient element and contaminating the electrical parts. For example, where a resilient element incorporating silicone compounds is present on an interposer for many months, the silicone may contaminate the leads of the interposer. This retards sonic or thermosonic bonding of the leads to contacts on a chip, and requires extra care in the bonding operation to assure satisfactory quality. By providing the resilient element separate from the microelectronic elements to be assembled, contamination of the conductive parts during storage is substantially eliminated and the formation of a satisfactory bond between the contacts and leads may be achieved.
In one embodiment, the porous resilient element includes a plurality of compliant pads whereby adjacent pads define channels running between the pads. In accordance with this particular embodiment, after the bonding step for connecting the electrical parts, a liquid encapsulant may be applied to fill the channels between adjacent pads, as described in the ""699 application. In a further embodiment, the resilient element includes a web interconnecting the plurality of compliant pads. In yet another embodiment, the resilient element includes elongated resilient strips which are oriented along the length-wise axis of the liner holding the strips.
Another aspect of the present invention provides methods of making resilient elements having one or more tacky surface regions. The resilient elements which are provided by these methods can be used in processes as described above, and in other processes for fabricating microelectronic packages. In a preferred method according to this aspect of the invention, a first liner including a tacky material is provided. The tacky material may be an adhesive, such as a pressure sensitive adhesive, or any other known material which may provide tack to the surface regions of the resilient element. A mass of a curable material, such as a silicone elastomer, is then screened or stencil printed onto the first liner so that a first surface region of the curable material is in contact with the first storage liner. A second storage liner including the tacky material may be abutted against a second surface region of the curable material so that the tacky material is in contact with the first and second surface regions of the curable material. The curable material is then subjected to a curing process which transforms the mass into a resilient element having first and second tacky surface regions. In another embodiment, only one liner having a tacky material is used to provide a resilient element having one tacky surface region. In further embodiments, the first liner may have a surface treatment formed thereon which ensures that the level of adhesion between the first liner and the resilient element is lower than the level of adhesion between the second liner and the resilient element so that the resilient element stays on the second liner when the first liner is being removed. It is also contemplated that the resilient element may be provided by cutting the resilient element out of a larger sheet of cured resilient material using a die press or a roll punch. In this embodiment, the die press or roll punch perforates the sheet to provide cut-out resilient elements which may be utilized as described above. The resilient element is then stored separate and apart from the microelectronic elements comprising the microelectronic package, for the reasons set forth above. Based upon such factors as the length of time that the resilient elements will be stored before being used and the nature of the microelectronic elements to which the resilient elements will be assembled, the resilient elements can be stored at different temperatures, such as room temperature or a cold storage temperature, and under different conditions.
Another aspect of the present invention provides methods of making a resilient element having one or more tacky surface regions whereby the resilient element may be a partially-cured resilient element having regions with different degrees of cure. The resilient elements which are provided by these methods can be used in the processes described above, and in other processes for fabricating microelectronic packages. In a preferred method according to this aspect of the invention, a first liner including a cure-inhibiting material is provided. A mass of a curable material, such as a silicone elastomer, is then screened or stenciled onto the first storage liner so that a first surface region of the mass is in contact with the first storage liner and an interior region of the mass is remote from the liner. The cure-inhibiting material, which may be an amine or chelating agent, inhibits complete curing of portions of the mass in contact with the cure-inhibiting material. A second storage liner, including a layer of a cure-inhibiting material may then be abutted against a second surface region of the mass so that the cure-inhibiting material of the first and second liners is in contact with the first and second surface regions of the mass, respectively. The mass is then subjected to a curing process which transforms the mass into a partially-cured resilient element having regions with different degrees of cure whereby the first and second surface regions of the resilient element which are in contact with the cure-inhibiting material have lesser degrees of cure than an interior region of the resilient element which is not in contact with the cure-inhibiting material. In another embodiment, only one liner having a cure-inhibiting material is used to provide a partially-cured resilient element having a first surface region which is cured to a lesser degree than the interior region of the resilient element. The partially-cured resilient element is then stored separately from the microelectronic elements comprising the microelectronic package, for the reasons set forth above.
In order to assemble a microelectronic package using the partially-cured resilient element described above, the resilient element is first removed from storage. Before assembling the partially-cured resilient element with a microelectronic element, a first liner film is removed from the resilient element to expose a first partially-cured surface region thereof. A catalyst or curing agent, such as a platinum-based curing agent, is then applied to the partially-cured resilient element, or one or both of the microelectronic elements and the resilient element is then assembled to a first microelectronic element so that the first surface region of the resilient element is in contact with the curing agent. In a similar fashion, the second liner film is removed from the partially-cured resilient element to expose a second surface region and the resilient element is then assembled to a second microelectronic element so that the second surface region of the resilient element is in contact with the curing agent. Most preferably, the step of assembling the partially-cured resilient element with at least one of the microelectronic elements is performed just shortly before the step of bonding the conductive parts to one another, typically less than 24 hours before the bonding step and most preferably less than one hour before the bonding step. Most preferably, the method according to this aspect of the invention further includes the step of additionally curing the resilient element after the assembling step, while the resilient element is in engagement with one or both of the microelectronic elements, as by applying a chemical curing agent or energy such as heat, ultraviolet or other radiant energy. In a further step, after bonding of the electrical parts, a liquid encapsulant may be applied to fill the spaces between the microelectronic elements and around the resilient element.
In another embodiment of a method of making the resilient elements described above, a liner film has first and second surfaces. A mass of a curable material is screened or stencil printed on the first surface of the liner so that a first surface region of the mass is in contact with the first surface of the liner. The second surface of the liner is then abutted against a second surface region of the mass which is remote from the first surface region of the mass. The above steps are performed repeatedly so as to provide a plurality of curable masses in engagement with the first liner. The method further includes the step of winding the first liner in a spiral to engage each one of the plurality of curable masses between the first surface of the liner on one turn of the spiral and the second surface of the liner on another turn of the spiral. The second surface of the liner may have a surface treatment formed thereon which ensures that the level of tack between the resilient element and the second surface of the liner is lower than the level of tack between the liner and the first surface of the resilient element. Thus, the resilient element will stay on the first liner when the second surface is being pulled away from the resilient element to prepare the resilient element for assembly to a microelectronic element. One such tack-reducing surface treatment is a synthetic flourine-containing resin sold under the trademark Teflon(copyright). In this embodiment, only one liner is required to cover both the first and second surface regions of the resilient element and the resilient elements are stored in a spiral-shaped configuration. In one preferred embodiment according to this invention, a tacky material such as a pressure sensitive adhesive is provided at the first and second surface regions. In another embodiment, the cure-inhibiting material described above is provided at the first and second surface regions of the resilient element to inhibit the cure of the first and second surface regions.
A further embodiment of the present invention provides resilient elements which can be either a plurality of compliant pads (i.e., a matrix of dots), whereby any two adjacent pads define a channel therebetween; a plurality of compliant pads connected by a web; a sheet having a plurality of compliant pads formed on opposite sides of the sheet; elongated resilient strips which are oriented in a direction parallel to the longitudinal axis of the storage liner; or a unitary structure having a square or rectangular shape. These resilient elements can be used in processes as described above, and in other processes for fabricating microelectronic packages. According to this aspect of the invention, the resilient elements are stored and shipped with liner films applied to the surface regions thereof. The liner films protect the surface regions from contamination and are further treated with a material for providing the surface regions with tack. For example, an adhesive material may be provided on the liners in contact with the surface regions of the resilient element, or a cure-inhibiting material may be provided on the liners to prevent curing of the surface regions of the resilient element. The resilient element with liners attached can then be stored separately from microelectronic elements until immediately before the juxtaposing, assembling and bonding steps described above. With respect to the use of a cure-inhibiting material, if a mass of curable elastomer, such as curable silicone, is exposed to the cure-inhibiting material during a curing process, then that portion of the mass in contact with the cure-inhibiting material will cure to a lesser degree than an interior region of the mass which is not in contact with the cure-inhibiting agent, e.g., the surface regions of the resilient element in contact with the cure-inhibiting agent will be cured to a lesser degree than the interior region of the resilient element.
The foregoing and other objects and advantages of the present invention will be better understood from the following detailed description of a preferred embodiment taken together with the attached figures.